(a) Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device provided with a test performing section capable of executing memory tests in a plurality of test modes.
(b) Description of the Related Art
In semiconductor integrated circuit devices including semiconductor memory devices, a function test is executed in a plurality of test modes. The test modes include one executed when a memory device is finished to a product and another executed when the product is installed in service. Hence, when a memory device is to be tested, it is necessary to input to the memory device a test mode selecting signal for selecting one of predetermined test modes as well as a test commanding signal for switching the memory device to a test operation mode.
In general, switching a memory device from a normal operation mode to a test operation mode is effected by inputting a predetermined address assigned to a test operation mode of the memory device via an address bus, simultaneously with inputting a test mode selecting signal via one of external test mode pins each corresponding to one of several test modes. However, with an increasing higher integration and finer pattern of a memory device, it is requested that the number of external pins be decreased.
In some memory devices, selection of one of several test modes is effected by inputting data for designating the one of the test modes through data bus instead of providing a test mode selecting signal via a corresponding external pin. In this ease, however, there is a drawback that the number of data items to be input for performing a test is large resulting in a complicated sequence of a memory tester for testing the memory device.